PCI (Peripheral Component Interconnect) Express is a high performance, general purpose I/O Interconnect defined for a wide variety of future computing and communication platforms. PCI Express maintains key PCI attributes, such as its usage model, load-store architecture, and software interfaces. PCI Express supports links between chips that may comprise x1, x2, x4, x8, x12, x16, or x32 lanes, and requires chips to support at least x1 links leaving chips to optionally support the other link widths. Further, PCI Express requires port interconnections between chips to be matched with some limited reordering. For example, chip A may support a x4 link using its ports 1-4, and chip B may support a x4 link using its ports 1-4. To create a x4 link between chip A and chip B, chip A ports 1-4 may be coupled respectively to chip B ports 1-4. PCI Express also indicates devices may optionally support lane reversal which allows for example chip A ports 1-4 to be respectively coupled to chip B ports 4-1. For further information regarding PCI Express, refer to PCI Express Base Specification Revision 1.0, Jul. 22, 2002 which may by obtained from the PCI-SIG at http://www.pcisig.org.